/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 * \file     Mcu_Clk.c                                                                                  *
 * \brief    AUTOSAR 4.3.1 MCAL Mcu Driver                                                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/08/01     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/
/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "Mcu_GeneralTypes.h"
#include "Mcu_Clk.h"
#include "Mcu_Ckgen.h"
#include "Mcu_CkgenDrv.h"
#include "Mcu_PllDrv.h"
#include "Mcu_Cfg.h"

#define MCU_START_SEC_CODE
#include "Mcu_MemMap.h"
/********************************************************************************************************
 *                                  Global Function Declarations                                        *
 *******************************************************************************************************/
/** *****************************************************************************************************
 * \brief Clk tree prepare interface.
 *          Used for generate clock tree's node by platform code,
 *          other code like app or driver should not use this ops.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_PrepareClockTree(const Mcu_ClkConfigType *clkPreparePtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPreparePtr - Pointer to clock tree config
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : Clk prepare interface.
 *                      Used for generate clock tree's node by platform code,
 *                      other code like app or driver should not use this ops.
 *                      you need consider clock divisible, to get high accuracy clock
 *                      frequency, you can get the actual frequency use Mcu_Ip_ClkGetRate api.
 *                      Be careful not to overclock and must be set according to TRM recommended flow.
 *                      Example: Mcu_PrepareClockTree(Mcu_ClockCfg->clkPrepare)
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
Std_ReturnType Mcu_PrepareClockTree(const Mcu_ClkConfigType *clkPreparePtr)
{
    Std_ReturnType errStatus = E_OK;
    uint32 cnt;

    if (NULL_PTR != clkPreparePtr)
    {
        /* pll config */
        if (NULL_PTR != clkPreparePtr->clkPllConfig)
        {
            for (cnt = 0U; cnt < (clkPreparePtr->clkPllConfig->configNum / 3U); cnt++)
            {
                errStatus = Mcu_Ip_PllDrvPrepare(clkPreparePtr->clkPllConfig->configNodes[(3U * cnt)].clkNode,
                                                 clkPreparePtr->clkPllConfig->configNodes[(3U * cnt)].rate,
                                                 clkPreparePtr->clkPllConfig->configNodes[((3U * cnt) + 1U)].rate,
                                                 clkPreparePtr->clkPllConfig->configNodes[((3U * cnt) + 2U)].rate,
                                                 clkPreparePtr->clkPllConfig->configNodes[(3U * cnt)].spreadConfig);

                if (E_OK != errStatus)
                {
                    break;
                }
            }
        }

        /* bus config */
        if ((E_OK == errStatus) && (NULL_PTR != clkPreparePtr->clkBusConfig))
        {
            for (cnt = 0U; cnt < clkPreparePtr->clkBusConfig->configNum; cnt++)
            {
                errStatus = Mcu_Ip_CkgenDrvBusSetRate(clkPreparePtr->clkBusConfig->configNodes[cnt].clkNode,
                                                      clkPreparePtr->clkBusConfig->configNodes[cnt].rate,
                                                      clkPreparePtr->clkBusConfig->configNodes[cnt].postDiv);

                if (E_OK != errStatus)
                {
                    break;
                }
            }
        }

        /* ip config */
        if ((E_OK == errStatus) && (NULL_PTR != clkPreparePtr->clkIpConfig))
        {
            for (cnt = 0U; cnt < clkPreparePtr->clkIpConfig->configNum; cnt++)
            {
                errStatus = Mcu_Ip_CkgenDrvIpSetRate(clkPreparePtr->clkIpConfig->configNodes[cnt].clkNode,
                                                     clkPreparePtr->clkIpConfig->configNodes[cnt].rate);

                if (E_OK != errStatus)
                {
                    break;
                }
            }
        }
    }
    else
    {
        errStatus = MCU_E_PARAM_POINTER;
    }

    return errStatus;
}

/** *****************************************************************************************************
 * \brief Clk set rate interface, set one clk node rate. will adaptively select parents.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_ClkSetRate(const Mcu_ClkNodeType *clkPtr, Mcu_ClkRateType rate, uint32 reserved1,
                                 uint32 reserved2, uint32 reserved3)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *                      rate - The clk rate to be set. for pll: pll vco rate.
 *                      reserved1 - for pll: ck0 rate.  for bus slice: cpu/axi/apb ratio. for ip slice: not used.
 *                      reserved2 - for pll: ck1 rate.  for bus slice: not used. for ip slice: not used.
 *                      reserved3 - for pll: spread config pointer. for bus slice: not used. for ip slice: not used.
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : Clock node frequency set. set one clk node(bus slice, ip slice or pll) rate.
 *                      will adaptively select parents.
 *                      This api not set the parent clock node, but will use the parent clock
 *                      node's rate to calculate divider's param.
 *                      you need consider clock divisible, to get high accuracy clock.
 *                      Some clk node may be not support Mcu_Ip_ClkSetRate api when it has child node.
 *                      This api always used for clock tree leaf node.
 *                      When setting the pll vco rate, ck0/ck1 should be set at the same time;
 *                      ck0/ck1 can also be set separately use this interface.
 *                      Be careful not to overclock and must be set according to TRM recommended flow.
 *                      Example: Mcu_Ip_ClkSetRate(CLK_NODE(g_ckgen_ip_enet1_tx), 250000000, 0, 0, 0)
 *                               Mcu_Ip_ClkSetRate(CLK_NODE(g_ckgen_bus_cr5_se_seip_r52), 600000000, CKGEN_BUS_DIV_4_2_1, 0, 0)
 *                               Mcu_Ip_ClkSetRate(CLK_NODE(g_pll1_vco), 2400000000, 400000000, 600000000, NULL_PTR)
 *                               Mcu_Ip_ClkSetRate(CLK_NODE(g_pll1_pll_ck0), 0, 400000000, 0, NULL_PTR)
 *                               Mcu_Ip_ClkSetRate(CLK_NODE(g_pll1_pll_ck1), 0, 0, 600000000, NULL_PTR)
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_ClkSetRate(const Mcu_ClkNodeType *clkPtr, Mcu_ClkRateType rate, uint32 reserved1,
                                 uint32 reserved2, uint32 reserved3)
{
    Std_ReturnType errStatus = MCU_E_PARAM_POINTER;

    if (NULL_PTR != clkPtr)
    {
        if ((CKGEN_PLL_CTRL_TYPE == clkPtr->type) || (CKGEN_PLL_CLK_TYPE == clkPtr->type))
        {
            errStatus = Mcu_Ip_PllDrvPrepare(clkPtr, rate, reserved1, reserved2,
            /* PRQA S 0306 1 */
                                 (const Mcu_PllSpreadConfigType *)reserved3);
        }
        else if ((CKGEN_SF_BUS_SLICE_TYPE == clkPtr->type) || (CKGEN_BUS_SLICE_TYPE == clkPtr->type))
        {
            /* PRQA S 4342 1 */
            errStatus = Mcu_Ip_CkgenDrvBusSetRate(clkPtr, rate, (Mcu_ClkBusRatioType)reserved1);
        }
        else if (CKGEN_IP_SLICE_TYPE == clkPtr->type)
        {
            errStatus = Mcu_Ip_CkgenDrvIpSetRate(clkPtr, rate);
        }
        else
        {
            errStatus = MCU_E_PARAM_CONFIG;
        }
    } /* else not needed */

    return errStatus;
}

/** *****************************************************************************************************
 * \brief Clk get rate interface, get one clk node rate(bus slice, ip slice, pll and xtal node).
 *
 * \verbatim
 * Syntax             : Mcu_ClkRateType Mcu_Ip_ClkGetRate(Mcu_ClkNodeType *clkPtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : Clock node frequency.
 *
 * Description        : Clock node frequency get.
 *                      node rate is calculated by register value.
 *                      return UINT32_MAX means error occurred.
 *                      Example: Mcu_Ip_ClkGetRate(CLK_NODE(g_ckgen_ip_enet1_tx))
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
uint32 Mcu_Ip_ClkGetRate(const Mcu_ClkNodeType *clkPtr)
{
    uint32 rate = UINT32_MAX;

    if (NULL_PTR != clkPtr)
    {
        if ((clkPtr->type == CKGEN_RC24M_TYPE) || (clkPtr->type == CKGEN_FS24M_TYPE))
        {
            rate = CKGEN_24M_RATE;
        }
        else if ((clkPtr->type == CKGEN_PLL_CTRL_TYPE) || (clkPtr->type == CKGEN_PLL_CLK_TYPE))
        {
            rate = Mcu_Ip_PllDrvGetRate(clkPtr);
        }
        else if (clkPtr->type == CKGEN_IP_SLICE_TYPE)
        {
            rate = Mcu_Ip_CkgenDrvIpGetRate(clkPtr);
        }
        else if ((clkPtr->type == CKGEN_BUS_SLICE_TYPE) || (clkPtr->type == CKGEN_SF_BUS_SLICE_TYPE))
        {
            rate = Mcu_Ip_CkgenDrvBusGetRate(clkPtr);
        }
        else
        {
            ; /* do nothing */
        }
    }

    return rate;
}

/** *****************************************************************************************************
 * \brief Clk get real rate interface, get one clk node rate(bus slice, ip slice).
 *
 * \verbatim
 * Syntax             : uint32 Mcu_Ip_ClkGetMonitorRate(const Mcu_ClkNodeType *clkPtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : Clock node frequency.
 *
 * Description        : Clock node real frequency by monitor get.
 *                      node rate is get by monitor.
 *                      return UINT32_MAX means error occurred.
 *                      Example: Mcu_Ip_ClkGetMonitorRate(CLK_NODE(g_ckgen_ip_enet1_tx))
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
uint32 Mcu_Ip_ClkGetMonitorRate(const Mcu_ClkNodeType *clkPtr)
{
    uint32 rate = UINT32_MAX;

    if (NULL_PTR != clkPtr)
    {
        if (clkPtr->type == CKGEN_IP_SLICE_TYPE)
        {
            rate = Mcu_Ip_CkgenDrvIpMonGetRate(clkPtr);
        }
        else if ((clkPtr->type == CKGEN_BUS_SLICE_TYPE) || (clkPtr->type == CKGEN_SF_BUS_SLICE_TYPE))
        {
            rate = Mcu_Ip_CkgenDrvBusMonGetRate(clkPtr);
        }
        else
        {
            ; /* do nothing */
        }
    }

    return rate;
}

/** *****************************************************************************************************
 * \brief Clk disable interface, disable one clk node if it has clock gate capacity.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_ClkDisable(const Mcu_ClkNodeType *clkPtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : Clk disable interface, disable one clk node if it has clock gate capacity.
 *                      Example: Mcu_Ip_ClkDisable(CLK_NODE(g_ckgen_gating_etmr1_pclk))
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_ClkDisable(const Mcu_ClkNodeType *clkPtr)
{
    Std_ReturnType errStatus = MCU_E_PARAM_POINTER;

    if (NULL_PTR != clkPtr)
    {
        errStatus = Mcu_Ip_CkgenDrvGatingDisable(clkPtr);
    }

    return errStatus;
}

/** *****************************************************************************************************
 * \brief Clk enable interface, enable one clk node if it has clock gate capacity.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_ClkEnable(const Mcu_ClkNodeType *clkPtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : errID
 *
 * Description        : Clk enable interface, enable one clk node if it has clock gate capacity.
 *                      Example: Mcu_Ip_ClkEnable(CLK_NODE(g_ckgen_gating_etmr1_pclk))
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_ClkEnable(const Mcu_ClkNodeType *clkPtr)
{
    Std_ReturnType errStatus = MCU_E_PARAM_POINTER;

    if (NULL_PTR != clkPtr)
    {
        errStatus = Mcu_Ip_CkgenDrvGatingEnable(clkPtr);
    }

    return errStatus;
}

/** *****************************************************************************************************
 * \brief Clk check gated interface.
 *
 * \verbatim
 * Syntax             : uint8 Mcu_Ip_ClkIsGated(const Mcu_ClkNodeType *clkPtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : clock gate state
 *
 * Description        : get the clock gate state in run mode.
 *                      return 1 means gated, 0 means active.
 *                      return 0xFFu means error occurred.
 *                      Example: isGated = Mcu_Ip_ClkIsGated(CLK_NODE(g_ckgen_gating_etmr1_pclk))
 *
 * \endverbatim
 * Traceability       : SW_SM006
 *******************************************************************************************************/
uint8 Mcu_Ip_ClkIsGated(const Mcu_ClkNodeType *clkPtr)
{
    uint8 isGated = 0xFFu;

    if (NULL_PTR != clkPtr)
    {
        isGated = Mcu_Ip_CkgenDrvGatingIsGated(clkPtr);
    } /* else not needed */

    return isGated;
}

/** *****************************************************************************************************
 * \brief pll check locked interface.
 *
 * \verbatim
 * Syntax             : uint8 Mcu_Ip_ClkIsLocked(const Mcu_ClkNodeType *clkPtr)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : clkPtr - Pointer to clock node
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : pll lock state
 *
 * Description        : get the pll lock state.
 *                      return 1 means in lock, 0 means unlock.
 *                      return 0xFFu means error occurred.
 *                      Example: isLock = Mcu_Ip_ClkIsLocked((CLK_NODE(g_pll1_vco))
 *
 * \endverbatim
 * Traceability       : SW_MCU_SM012
 *******************************************************************************************************/
uint8 Mcu_Ip_ClkIsLocked(const Mcu_ClkNodeType *clkPtr)
{
    uint8 isLocked = 0xFFu;

    if (NULL_PTR != clkPtr)
    {
        isLocked = Mcu_Ip_PllDrvIsLocked(clkPtr);
    } /* else not needed */

    return isLocked;
}

#define MCU_STOP_SEC_CODE
#include "Mcu_MemMap.h"
/* End of file */
